This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
FIG. 1 illustrates a conventional level shifter 100 as known in the art. In latest technologies, the trend is to lower core voltage (VDD) of SOC (System On a Chip) devices to reduce power consumption. In general purpose I/O (input/output) interfaces, standard level shifter designs only use thick oxide devices 102. This is done to avoid risk of having some transistors (N0, N1) stressed above technology boundaries.
In some I/O interfaces, the conventional level shifter 100 refers to a circuit that is typically used to translate a signal from VDD (core supply domain) to DVDD (I/O supply domain). However, when the core voltage VDD is substantially low (e.g., 0.5V and below), VDD is near or below a threshold voltage (VTh) of thick oxide transistors (N0, N1).
In reference to FIG. 1, the VTh of the thick oxide transistors NO and N1 can be higher than the input voltage IN, INB received at their gates. Therefore, the conventional level shifter 100 is typically no longer functional when the core voltage VDD is substantially low (e.g., 0.5V and below), and in some cases, the conventional level shifter 100 can fail to operate or function properly at substantially low voltages.